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PCD6 Series controllers

PCD6 programmable controller

Although now obsolete some spares and replacement processors are still available either directly from MACOL or from another source that we may be able to help you locate.

For customers wishing to update to a modern controller we are able to reverse engineer undocumented software and re-write it for the replacement system. This is often the most cost-effective solution offering like-for-like functionality with minimum downtime.

The manual for the PCD6 series is available for download as a ZIP file here.

Processor modules 1 to 7 Equipped with bit and word processor, communication processor and LAN2-processor as required (only 1 LAN2-processor per system).

Execution time approx. 6 μs per logic instruction (directly without a process image).

User memory RAM battery-buffered or EPROM with ..R1../..R5.. 64 K program lines (of 32 bits) or up to 256 K text or data characters or mixed. With ..R2../..R6.. 256 K program lines (of 32 bits) or up to 1 M text or data characters or mixed
Separate data blocks corresponding to max. 192 K register (program and text appropriately reduced)

Number of inputs Max. 256 in the same rack unit, and outputs 1280 in the same rack (with 5 rack units each of 256 I/O)
5120 in 4 racks (each with 5 rack units). Address range 0...8191.

Serial interfaces 4 per communications processor, i.e. max. 28 interfaces for 7 processor modules. 4 per single processor ..M540.

Types of interface RS 232c, RS 422/485, 20 mA current loop.

Flags 8192 (can be divided into volatile and non-volatile flags).

Timers/counters 1600, 31 bits, division is programmable (timers are always volatile, while counters are always non-volatile).

Time base Programmable in the range 10 ms to 10 s

Data register 4096 x 32 bits (non-volatile) loadable in the user program or externally from disk, using the whole user program the data capacity will reach max. 1 Mbyte (see user memory).


Data formats Decimal, hexadecimal, BCD, binary or floating-point (exponential representation).

Index register 16 x 13 bits (per processor).